1. Field of the Invention
The present invention is generally in the field of fabrication of semiconductor devices. More particularly, the present invention is in the field of fabrication of heterojunction bipolar transistors.
2. Related Art
In a silicon-germanium (xe2x80x9cSiGexe2x80x9d) NPN heterojunction bipolar transistor (xe2x80x9cHBTxe2x80x9d), a thin P type silicon-germanium layer is grown as the base of a bipolar transistor on a silicon wafer. The silicon-germanium NPN HBT has significant advantages in speed, frequency response, and gain when compared to a conventional silicon bipolar transistor. Cutoff frequencies in excess of 100 GHz, which are comparable to the more expensive gallium-arsenide based devices, have been achieved for the silicon-germanium NPN HBT. Previously, silicon-only devices have not been competitive for use where very high speed and frequency responses are required.
The higher gain, speed and frequency response of the silicon-germanium NPN HBT are possible due to certain advantages of silicon-germanium, such as a narrower band gap and reduced resistivity. Silicon-germanium may be epitaxially grown on silicon wafers using conventional silicon processing and tools which allow one to engineer device properties such as band gap, energy band structure and mobilities. For example, it is known in the art that grading the concentration of germanium in the silicon-germanium base builds into the HBT device an electric field which accelerates the carriers across the base, thereby increasing the speed of the HBT device compared to a silicon-only device.
One method for fabricating silicon-germanium devices is by chemical vapor deposition (xe2x80x9cCVDxe2x80x9d). In a typical silicon-germanium HBT fabrication process, for example, a reduced pressure CVD technique, or xe2x80x9cRPCVDxe2x80x9d, is used for growing silicon-germanium epitaxially on a silicon wafer. The RPCVD process allows for a controlled grading of germanium across the base layer.
When grown epitaxially on a silicon surface, silicon-germanium crystallizes as a single-crystal layer. The single-crystal silicon-germanium can be deposited over an N type collector region and doped with P type dopants such as boron to function as the P type base of a silicon-germanium NPN HBT. Doping of the epitaxial growth is achieved by adding a precursor for dopant to the gas flow across the silicon surface during the RPCVD process. For example, the precursor for boron is B2H6. Subsequently, an N type emitter can be fabricated over the silicon-germanium single-crystal P type base to complete fabrication of a vertical silicon-germanium NPN HBT. As already noted, speeds in the range of approximately 100 GHz have been demonstrated for silicon-germanium devices, such as the NPN HBT.
As is known in the art, the fabrication of a silicon-germanium NPN HBT involves more steps than the basic steps described above. The simplified process for fabricating a silicon-germanium NPN HBT described above leaves out such steps as additional doping and etching steps, among others. which can add considerable cost to semiconductor fabrication. Moreover, each step can comprise various sub-steps, for example, masking, washing and cleaning steps, which also increase the cost of fabrication.
A similar sequence of steps used for fabricating a vertical silicon-germanium NPN HBT can be used to fabricate a vertical silicon-germanium PNP HBT. In other words, a layer of silicon-germanium can be deposited epitaxially on a silicon wafer over a P type collector region and doped with N type dopants to function as an N type base in a PNP HBT. Subsequently, a P type emitter can be fabricated on the silicon-germanium base. However, unlike the NPN transistor, the PNP transistor is not a high performance device. The PNP transistor is generally slower than its NPN counterpart and functions typically more as an active bias device, rather than a speed device. And because of its relatively low performance compared to NPN devices, the PNP device is, under most circumstances, less desirable, and the high cost of fabricating the PNP device using the method described above makes it less feasible.
An alternative method for fabricating a silicon-germanium PNP HBT takes advantage of some of the steps utilized in the fabrication of an NPN transistor in order to fabricate a PNP transistor concurrently. For example, in one region of a silicon wafer, a P type silicon-germanium layer deposited over an N type collector region functions as the base of an NPN device; at the same time, the same P type silicon-germanium layer can function as an emitter of a PNP device in another region of the wafer where it is deposited over an n-well. which functions as the base of the PNP device. Further, a region adjacent to the n-well can be doped with P type dopants to function as a P type collector, resulting in the formation of a lateral PNP transistor where the silicon germanium layer functions as a P type emitter. The benefit of incorporating steps for fabricating an NPN device into the fabrication process for a PNP device is the reduction in process complexity and costs, because certain processing steps needed to fabricate a separate P type emitter for a PNP transistor are avoided.
As stated above, silicon-germanium crystallizes as single-crystal when deposited epitaxially on a silicon surface. Thus, when silicon-germanium is deposited over an n-well and doped with P type dopants to function as the emitter of a PNP HBT, the resulting emitter is single-crystal P type emitter. A silicon-germanium PNP HBT comprising a single-crystal emitter has unacceptably low gain, or xcex2, typically in the order of 1/10 to 1/100. Gain, simply stated, is the ratio of collector current, Ic. divided by base current, Ib, i.e. gain equals Ic/Ib. The poor gain can be attributed to a lack of blocking injection control at the emitter-base interface which means that it is just as likely for electrons to flow from the emitter to the base, as it is for holes to migrate in the opposite direction. Thus, although the cost for fabricating a silicon-germanium PNP HBT is reduced by incorporating NPN HBT processing steps, the PNP device resulting from this method has unacceptably low gain.
There is thus a need in the art for method for fabricating a lateral silicon-germanium PNP HBT having a high gain and a low manufacturing cost.
The present invention is directed to method for fabricating lateral PNP heterojunction bipolar transistor and related structure. The invention results in a PNP heterojunction bipolar transistor having a high gain and a low manufacturing cost.
According to one embodiment of the invention, a dielectric layer is deposited over an n-well. For example, the dielectric layer can be silicon dioxide, silicon nitride or a low-k dielectric. Subsequently, the dielectric layer is etched to fabricate an opening over the n-well. An interfacial oxide layer is next formed in the opening. The thickness of the interfacial oxide layer, which is directly related to the transistor""s gain, can be between approximately 9 Angstroms and approximately 13 Angstroms. Moreover, the interfacial oxide layer can comprise. for example, silicon dioxide with a density between approximately 1*1015 and 3*1015 atoms per square centimeter. Thereafter, a semiconductor layer, which can comprise amorphous silicon for instance, is deposited over the interfacial oxide layer. In one embodiment, the semiconductor layer is doped with a P type dopant. A layer of silicon-germanium is then grown over the semiconductor layer.
In another embodiment of the invention, a dielectric layer is deposited over an n-well. For example, the dielectric layer can comprise silicon dioxide, silicon nitride or a low-k dielectric. The dielectric layer is then etched to fabricate a gap over the n-well between the dielectric layer and an oxide region. The oxide region can be, for instance, field oxide, shallow trench isolation oxide or local oxidation of silicon oxide (xe2x80x9cLOCOSxe2x80x9d). Subsequently, a layer of silicon-germanium is grown in the gap. The gap has a gap width which satisfies a pre-determined relation to the thickness of the layer of silicon-germanium. For example, gap width can be restricted to less than twice the thickness of the layer of silicon-germanium. Moreover, a plurality of gaps can be etched in the dielectric layer, with each of the plurality of gaps having a similarly restricted gap width. Thereafter, a layer of silicon-germanium is grown in the plurality of gaps.